The present invention relates to bridges for interconnecting computer buses of differing types, and more particularly to conversion of an address received on a big-endian bus for use on a little-endian bus.
Computer architectures typically consist of a number of elements, such as one or more processors, memory units, and various input/output (I/O) devices, all coupled together by means of a shared computer bus. In order to facilitate the interconnection of system components that are made by independently operating manufacturers, a number of bus architectures have been standardized. Each bus architecture specifies the necessary electrical and functional characteristics for allowing one device to communicate with others on the same bus.
Bus characteristics can vary widely from one standard architecture to another. For example, some bus architectures include separate address and data lines, while others use shared lines that are time multiplexed between representing address and data information. Regardless of the physical manifestation, however, a typical computer system bus is conceptually divided into an address bus, a data bus and a control bus. A bus transaction is a complete exchange between two bus devices, and typically comprises both an address phase, during which address information is presented on the address bus, and a data phase during which data information is presented on the data bus. The data phase of a bus transaction may follow the address phase of the same transaction in ordered succession, without any other data phase of any other bus transaction intervening. In such a case, the system bus is said to be "tightly ordered." Small computer systems are, as a general rule, tightly ordered. An example of a standardized tightly ordered bus architecture is the PCI local bus. A complete description of the PCI local bus is presented in the PCI Local Bus Specification, Review Draft Revision 2.1, published Oct. 21, 1994 by the PCI Special Interest Group, P.O. Box 14070, Portland, Oreg. 97214, which is incorporated herein by reference in its entirety.
By contrast, in some minicomputer and mainframe computers, and more recently in some small computer architectures, buses are "loosely ordered" such that, between the address phase of a bus transaction and the corresponding data phase, other data phases of other bus transactions may occur. The ability of the bus to allow the address bus and data bus to have different masters at the same time is called "split-bus transaction capability". The PowerPC.TM. computer architecture, co-developed by Apple Computer, utilizes a loosely ordered system bus that provides split-bus transaction capability.
PowerPC.TM. machines currently sold by Apple are based largely on the Motorola MPC601 RISC microprocessor. The MPC601 permits separate address bus tenures and data bus tenures, where tenure is defined as the period of bus mastership. In other words, rather than considering the system bus as an indivisible resource and arbitrating for access to the entire bus, the address and data buses are considered as separate resources, and arbitration for access to these two buses may be performed independently. A transaction, or complete exchange between two bus devices, is minimally comprised of an address tenure; one or more data tenures may also be involved in the exchange. The address and data tenures of each access request must be arbitrated separately from one another. However, the request for a data bus tenure is not made explicitly, but is instead implied by the occurrence of a corresponding address bus request/transaction. More information about the particulars of the system bus in the MPC601 RISC microprocessor may be found in the PowerPc 601 RISC Microprocessor User's Manual, published by Motorola in 1993, which is incorporated herein by reference in its entirety. Another loosely coupled system bus is described in U.S. patent application Ser. No. 08/432,620, which was filed by James Kelly et al. on May 2, 1995, and entitled BUS TRANSACTION REORDERING USING SIDEBAND INFORMATION SIGNALS, and which is incorporated herein by reference in its entirety. The bus that is described in U.S. patent application Ser. No. 08/432,620 is a superset of the conventional PowerPC.TM. 601 microprocessor interface, and is known as the Apple RISC Bus.TM., or ARBus.TM..
Another difference between some bus architectures in general, and between the ARBus.TM. and the PCI bus in particular, relates to their endian-ness. The concept of endian-ness derives from the fact that computer representations of scalars (individual computational data items) are not indivisible. If they were, then the order of bits or groups of bits within the smallest addressable unit of memory would be irrelevant, because nothing could be observed about such order. However, as implemented in most computer systems, order does matter because scalars can be made up of more than one addressable unit of memory, despite the fact that the processor and programmer regard them as indivisible quantities.
Consider, for example, the PowerPC.TM. 601 processor, which is capable of handling a 64-bit double word. If the 64-bit double word were the smallest addressable unit, then there would be no question of the order of bytes within double words. All scalar transfers between registers and system memory would be for double words and the address of the byte containing the high-order eight bits of a scalar would be no different from the address of a byte containing any other part of the scalar.
However, in actuality, the smallest addressable memory unit in the PowerPC.TM. processor is the byte (8 bits), and most scalars are composed of groups of bytes. When a 32-bit scalar is moved from a register to memory, it occupies four consecutive byte addresses, and a decision must be made regarding the order of these bytes in these four addresses.
The choice of byte ordering is arbitrary. Although there are 24 possible permutations of four bytes, only two are practical: big-endian and little-endian. Big-endian ordering assigns the lowest address to the highest-order eight bits of the scalar. The name "big-endian" derives from the fact that the big end of the scalar, considered as a binary number, comes first in memory. By contrast, little-endian byte ordering assigns the lowest address to the lowest-order (rightmost) 8 bits of the scalar. The little end of the scalar, considered as a binary number, comes first in memory.
The difference between big- and little-endian representations is illustrated in FIGS. 1A and 1B. The storage in memory of a scalar comprising eight bytes of data is illustrated in both figures. As shown in FIG. 1A, in a big-endian system the most significant byte (MSB) is stored at address n, the next byte is stored at address location n+1, and so on until the least significant byte (LSB) is stored at address location n+7. By contrast, the little-endian system illustrated in FIG. 1B shows that, for the same scalar, address n refers to the LSB, with increasing addresses referring to more significant bytes, so that the MSB is stored at address location n+7.
The discussion of endian-ness is pertinent to bus architectures, because modern buses are typically wide enough to transfer multiple bytes in a single data transaction, or "beat". Since all data transfers are accompanied by an associated address (typically a byte-address in most microcomputers), it is important, for proper reception of data, to know which byte (i.e., MSB, LSB or other) the address refers to.
Another address-related difference between standardized buses relates their addressing schemes. An addressing scheme would be a trivial matter if each data transfer comprised as many bytes as the bus was capable of handling at one time (i.e., the width of the data bus). In such a case, one would only have to clock in data from the entire bus, and then use the received address and knowledge of the bus' endian characteristic to figure out where the data goes. However, it is often the case that a bus architecture will allow for the transfer of fewer bytes of data than the bus is capable of handling in a single beat. Accordingly, the addressing scheme must also include some method for detecting which byte lanes on the bus contain the transferred data. In the case of the ARBus.TM., whose dedicated data lines are 64 bits wide, the addressing scheme includes providing a 32-bit wide address, the lower three bits of which designate the byte lane (in big-endian notation) in which the first transferred byte will be found. Three separate control lines, that are also part of the ARBus.TM., designate the total number of bytes that are being transferred during this data transfer. The three lines are encoded so that the binary value 3'b001 designates one byte of data, the binary value 3'b010 designates two bytes of data, and so on up to 3'b111 which designates seven bytes of data being transferred. In accordance with the ARBus.TM. design, the value 3'b000 designates eight rather than zero bytes transferred.
By comparison, the PCI bus comprises a little-endian 32-bit wide address-data bus. That is, the address and data information are transferred over a common set of lines during separate bus phases. The transfer of a 64-bit quantity on the PCI bus would first require the communication of a start address (corresponding to the LSB of the first 4-byte quantity to be received), followed by two data beats, each conveying thirty-two bits of data. As a little-endian system, the data transferred during the first beat has a lower address than that of the data received in the second beat. Consequently, a receiving agent on a PCI bus would have to increment the received address by 4 when receiving the second beat of the 64-bit transfer.
To complicate things further, the PCI bus architecture does not require that all thirty-two bits of the bus convey meaningful data during any particular data phase. In order to indicate which byte lanes contain valid data, the PCI bus architecture defines four parallel lines, designated "byte enable signals" (BE[3:0]), which are asserted during the data phase, and which are used for clocking in data only from the indicated byte lanes; data on other byte lanes is ignored. (The BE[3:0] signals are multiplexed with a bus command, which is transmitted during the address phase. A description of the various PCI bus commands is beyond the scope of this discussion.)
In view of the many differences between standardized bus architectures, it is apparent that devices that are designed for one bus type cannot be utilized in a system built around an incompatible bus type without the provision of a mechanism for interconnecting the two buses. Such means for interconnection are known in the art, and are referred to as bus bridges.
When it is desired to interconnect two buses having respectively different methods for indicating addresses of transferred data (e.g., byte address plus size indicators versus word (16-bits) address plus byte enable signals), the bridge must perform a conversion of one type of signal to another. When those two buses have different endian-ness characteristics as well, the task is further complicated by the need to actually transform, say, a big-endian address appearing on one side of the bridge into a valid little-endian address on the other side of the bridge. For example, consider the three-byte scalar 201 depicted in FIG. 2A. When it arrives on an ARBus.TM. side of the bridge, it will have a hexadecimal address equal to 32'hxxxx xxx1 (or alternatively 32'hxxxx xxx9), where "x" indicates "don't care" values. Furthermore, the corresponding size indicator will be set to 3'b011, to indicate the presence of three meaningful bytes of data on the bus. When the other port of the bridge is connected to a PCI bus, it is the job of the bridge address conversion mechanism to output one data beat with an address equal to 32'hxxxx xxx4 (or alternatively 32'hxxxx xxxC), and the four byte enable signals set to 4'b1000 (assuming that the byte enable signals are active low).
As another example, consider the six-byte scalar 203 depicted in FIG. 2B. When the scalar 203 arrives on an ARBus.TM. side of the bridge, it will have a hexadecimal address equal to 32'hxxxx xxx2 (or alternatively 32'hxxxx xxxA). Furthermore, the corresponding size indicator will be set to 3'b110, to indicate the presence of six meaningful bytes of data on the bus. When the other port on the bus bridge is connected to a PCI bus, it is the job of the bridge address conversion mechanism to output an address followed by two data beats. In this case, the address will specify 32'hxxxx xxx0 (or alternatively 32'hxxxx xxxC). During the first data beat, the four byte enable signals will be set to 4'b0000 (again assuming signals that are active low), to indicate meaningful data on all four of the byte lanes. During the second data beat, the two MSBs 207 are transferred on the 32-bit wide PCI bus with the four byte enable signals set to 4'b1100 (again, active low signals). Consequently, during the second beat only two bytes will be received by the agent attached to the PCI bus. Notice that no address accompanied the second data beat. It is the responsibility of the receiving agent to know that the data received in the second beat has a base address of 32'hxxxx xxx4 (or alternatively 32'hxxxx xxxC), with possible offsets determined by the byte enable signals.
Finally, it is noted that in some bus bridges, an "address invariance" mode is available, whereby an end-for-end byte swap of the data received on one bus is performed before placing that data on the other bus. The address conversion mechanism must be able to take this into account when deriving converted address and byte enable signals.